1. Field of the Invention
The present invention relates to a submicron gate electrode of a semiconductor device, and more particularly to a method for fabricating a self-aligned submicron gate electrode using an anisotropic etching process.
2. Description of the Related Art
Remarkable development recently made in radio communication fields has resulted in an increased demand for ultrahigh broadband communication networks. An exemplary one of such networks is a network for local multipoint distribution services in which audio, video conference, and digital signals are simultaneously transmitted at a bandwidth of 1.3 GHz within a service area of 2 to 7 Km in radius, using a 28 GHz xe2x80x9cKa-bandxe2x80x9d. In order to construct such an ultrahigh broadband communication network, it is very important to develop ultrahigh-frequency devices operating the above mentioned frequency band while achieving a miniature and high performance of devices. To this end, active research efforts have been made. In particular, devices including submicron gates have been highlighted.
Conventional techniques associated with submicron gates are disclosed in U.S. Pat. No. 5,288,645 (entitled xe2x80x9cMethod of making a mushroom-shaped gate electrode of semiconductor device), and U.S. Pat. No. 5,053,348 (entitled xe2x80x9cFabrication of self-aligned, T-gate HEMTxe2x80x9d). However, these techniques require an expensive exposure process, such as an electron beam writing process or a stepped exposure process, to form a submicron gate. Furthermore, these techniques involve execution of a number of semiconductor processes including repeated exposure, deposition and etching. In order to obtain a desired self-alignment of the submicron gate, diverse semiconductor processes for forming, for example, sidewalls, should be conducted.
Another conventional technique is known in association with submicron gates. For example, the following references discloses a method in which an electron beam writing process is repeatedly used to form a submicron gate, and sidewalls are formed using a dielectric material to obtain a self-alignment of the submicron gate.
[Reference]
1. A dielectric-defined process for the formation of T-gate field-effect transistors. G. M. Metze. IEEE MGWL. Vol. 1, No. 8, August 1991.
2. High-Frequency low power IC""s in a scaled submicrometer HBT technology. IEEE MTT. Vol. 45, No. 12, December 1997.
However, this technique requires an expensive exposure process, such as an electron beam writing process or a stepped exposure process, or a complex process involving a formation of sidewalls, to form a self-aligned submicron gate. As a result, there is a drawback of an increase in the manufacturing costs.
Therefore, the present invention has been made in view of the above mentioned problems, and an object of the present invention is to provide a submicron gate fabrication method capable of fabricating a reliably self-aligned submicron gate using a simplified process.
In order to accomplish this object, the present invention provides a method for fabricating a submicron gate comprising the steps of: (a) laminating a dummy emitter defining a dummy emitter region over a heterojunction bipolar transistor structure including layers sequentially formed over a semiconductor substrate to define a base region, an emitter region, and an emitter cap region, respectively; (b) defining a line having a width of about 1 micron on the dummy emitter by use of a photoresist while using a contact aligner; (c) selectively anisotropic etching the dummy emitter at a region where the line is defined, to allow the dummy emitter to have an etched portion having a bottom surface with a width less than the width of the line defined by the photoresist; and (d) depositing a contact metal on the etched portion of the dummy emitter, thereby forming a gate.
A contact metal is deposited over the resulting structure with the gate, thereby self-aligning the gate.
In the formation of a base electrode involved in the fabrication of an HBT device, the present invention also provides an effect of reducing the distance between a base and an emitter as much as possible, thereby achieving a reduction in base resistance, in that it enables a self alignment using a V-shaped submicron gate.